The invention relates to a high resolution digital analog conversion circuit.
Digital to analog converters (DAC) available today have usually up to 16 bit resolution. Converters with higher resolution tend to be expensive and/or are very slow.
In some applications converters having a high precision and monotonicity are required. For example, nanopositioning and servo control applications require a high resolution DAC, with particularly high monotonicity. Typical requirements are for a DAC with a resolution and monotonicity of at least 20 bits and an analog bandwidth of at least 5 kHz.
One way to increase the resolution is to use 16 bit conversion and to switch its value fed to the DAC between two adjacent 16 bit values, thereby obtaining pulse width modulation with the least significant bit. This allows to achieve a resolution of n bits with a DAC having a resolution of m<n bits. The n bit input value to the digital analog conversion circuit is fed to a control circuit, which converts the input value to a series of different m bit control values and feeds the control values to the DAC. The DAC generates a time-dependent raw voltage whose average is equal to the desired output voltage.
The noise generated by the modulation can be suppressed by means of a low-pass filter. In theory the update frequency of a 16 bit converter has to be more than 16 times higher than the cut-off frequency to achieve a resolution off 20 bit.
The sigma delta architecture is more advanced than the simple pulse width modulation technique since it will distribute the modulation noise to a broad high frequency range.
These methods suffer from glitch effects that are generated when a DAC switches through a major bit transition. For example, when the input value to the DAC changes from 0111111111111111 to 100000000000000, 15 current sources within the DAC have to be switched off and one has to be switched on. The timing of this switching process is never perfect and therefore an intermediary pulse is generated, a so-called “glitch”. This type of glitch does not have equal magnitude when incrementing and decrementing the input value. Hence, using pulse width modulation over a major bit transition generates an undesired DC error in the result.
One way to overcome this is to use two sigma-delta modulated DACs fed with input values of opposite sign and to form the difference voltage between their outputs. Even though this yields better results, two DACs of a specific design will exhibit slightly different glitch values, and a small DC offset will remain.